연구실적

• A Unified Current-Voltage Model for Metal Oxide-Based Resistive Random-Access Memory Materials, 2023, v.16 no.1, 182
  SCIE Scopus dColl.
• An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network IET CIRCUITS DEVICES & SYSTEMS, 2023, v.2023, 1052063
  SCIE Scopus dColl.
• Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors IEEE Access, 2023, v.11, 15909-15920
  SCIE Scopus dColl.
• Dependency of Spiking Behaviors of an Integrate-and-fire Neuron Circuit on Shunt Capacitor JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2023, v.23 no.3, 189-195
  SCIE Scopus KCI dColl.
• Analysis of hump effect in tensile-stressed a-IGZO TFT using TCAD simulation 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021, 2021 , 9369787
  Scopus dColl.
• Analysis of the transient body effect model for an LTPS TFT on a plastic substrate Solid-State Electronics, 2021, v.175, 107948
  SCIE Scopus dColl.
• Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM MICROMACHINES, 2021, v.12 no.10, 1209
  SCIE Scopus dColl.
• New simulation method for dependency of device degradation on bending direction and channel length Materials, 2021, v.14 no.20, 6167
  SCIE Scopus dColl.
• Selected Bit-Line Current PUF: Implementation of Hardware Security Primitive Based on a Memristor Crossbar Array IEEE ACCESS, 2021, v.9, 120901-120910
  SCIE Scopus dColl.
• Analysis of Organic Light-Emitting Diode SPICE Models with Constant or Voltage-Dependent Components JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2020, v.20 no.8, 4773-4777
  SCIE Scopus dColl.
• Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM MICROMACHINES, 2020, v.11 no.11, 952
  SCIE Scopus dColl.
• Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM MICROMACHINES, 2020, v.11 no.2, 228
  SCIE Scopus dColl.
• Charge Based Current-Voltage Model for the Silicon on Insulator Junctionless Field-Effect Transistor JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2020, v.20 no.8, 4920-4925
  SCIE Scopus dColl.
• Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2020, v.20 no.8, 4730-4734
  SCIE Scopus dColl.
• Multibit-Generating Pulsewidth-Based Memristive-PUF Structure and Circuit Implementation ELECTRONICS, 2020, v.9 no.9, 1446
  SCIE Scopus dColl.
• Optimization considerations for short channel poly-Si 1T-DRAM Electronics (Switzerland), 2020, v.9 no.6, 1-11
  SCIE Scopus dColl.
• A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency IEEE ELECTRON DEVICE LETTERS, 2019, v.40 no.4, 562-565
  SCIE Scopus dColl.
• Analysis of Cell Variability Impact on a 3-D Vertical RRAM (VRRAM) Crossbar Array Using a Modified Lumping Method IEEE Transactions on Electron Devices, 2019, v.66 no.1, 759-765
  SCIE Scopus dColl.
• Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2019, v.34 no.10, 105007
  SCIE Scopus dColl.
• Analysis of the Memristor-Based Crossbar Synapse for Neuromorphic Systems JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2019, v.19 no.10, 6703-6709
  SCIE Scopus dColl.
• Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect IEEE ELECTRON DEVICE LETTERS, 2019, v.40 no.4, 566-569
  SCIE Scopus dColl.
• Memristor Neural Network Training with Clock Synchronous Neuromorphic System MICROMACHINES, 2019, v.10 no.6
  SCIE Scopus dColl.
• Analysis of Read Margin and Write Power Consumption of a 3-D vertical RRAM (VRRAM) Crossbar Array IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, v.6 no.1, 1192-1196
  SCIE Scopus dColl.
• Analysis of read margin of crossbar array according to selector and resistor variation International Conference on Electronics, Information and Communication, ICEIC 2018, 2018, v.2018-January, 1-3
  Scopus dColl.
• New modeling method for the dielectric relaxation of a DRAM cell capacitor Solid-State Electronics, 2018, v.140, 29-33
  SCIE Scopus dColl.
• Read margin analysis of crossbar arrays using the cell-variability-aware simulation method Solid-State Electronics, 2018, v.140, 55-58
  SCIE Scopus dColl.
• A Guideline for electron mobility enhancement in uniaxially-strained (100)/(100) and (110)/(110) fin field effect transistors Journal of Nanoscience and Nanotechnology, 2017, v.17 no.5, 2999-3004
  SCIE Scopus dColl.
• A New Method for Determining the Subgap Density of States in n-/p-Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistors JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2017, v.17 no.5, 2951-2958
  SCIE Scopus dColl.
• The effect of a source-contacted light shield on the electrical characteristics of an LTPS TFT Semiconductor Science and Technology, 2017, v.32 no.8
  SCIE Scopus dColl.
• A Survey on the Modeling of Magnetic Tunnel Junctions for Circuit Simulation ACTIVE AND PASSIVE ELECTRONIC COMPONENTS, 2016, v.2016
  Scopus dColl.
• A new bias scheme for a low power consumption ReRAM crossbar array Semiconductor Science and Technology, 2016, v.31 no.8
  SCIE Scopus dColl.
• An analysis of the read margin and power consumption of crossbar ReRAM arrays IEEE Region 10 Annual International Conference, Proceedings/TENCON, 2016, v.2016-January
  Scopus dColl.
• Analysis of stress effect on (110)-oriented single-gate SOI nMOSFETs using a silicon-thickness-dependent deformation potential Journal of Nanoscience and Nanotechnology, 2016, v.16 no.5, 5150-5154
  SCIE Scopus dColl.
• Analysis of the effect of the density of states on the characteristics of thin-film transistors IEEE Region 10 Annual International Conference, Proceedings/TENCON, 2016, v.2016-January
  Scopus dColl.
• Analysis of the substantial reduction of strain-induced mobility enhancement in (110)-oriented ultrathin double-gate MOSFETs Applied Physics Express, 2016, v.9 no.1
  SCIE Scopus dColl.
• Anomalous capacitance characteristics of TFTs with LDD structures in the saturation region SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2016, v.31 no.5
  SCIE Scopus dColl.
• Guideline model for the bias-scheme-dependent power consumption of a resistive random access memory crossbar array Japanese Journal of Applied Physics, 2016, v.55 no.4
  SCIE Scopus dColl.
• ReRAM Crossbar Array: Reduction of Access Time by Reducing the Parasitic Capacitance of the Selector Device IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, v.63 no.2, 873-876
  SCIE Scopus dColl.
• Switching Time and Stability Evaluation for Writing Operation of STT-MRAM Crossbar Array IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, v.63 no.10, 3914-3921
  SCIE Scopus dColl.
• Advanced Circuit-Level Model for Temperature-Sensitive Read/Write Operation of a Magnetic Tunnel Junction IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, v.62 no.2, 666-672
  SCIE Scopus dColl.
• Analysis of stress-induced mobility enhancement on (100)-oriented single- and double-gate n-MOSFETs using silicon-thickness- dependent deformation potential SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2015, v.30 no.4
  SCIE Scopus dColl.
• Investigation of power dissipation for ReRAM in crossbar array architecture 2014 14th Annual Non-Volatile Memory Technology Symposium, NVMTS 2014, 2015, 27-29 Oct 2014
  Scopus dColl.
• Anomalous drain-induced barrier lowering effect of thin-film transistors due to capacitive coupling voltage of light-shield metal Electronics Letters, 2014, v.50 no.15, 1093-1095
  SCIE Scopus dColl.
• Optimization of uniaxial stress for high electron mobility on biaxially-strained n-MOSFETs SOLID-STATE ELECTRONICS, 2014, v.94, 23-27
  SCIE Scopus dColl.
• Substrate Doping Concentration Dependence of Electron Mobility Enhancement in Uniaxial Strained (110)/< 110 > nMOSFETs JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, v.14 no.5, 518-524
  SCIE KCI dColl.
• Temperature Dependence of Electron Mobility in Uniaxial Strained nMOSFETs JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, v.14 no.2, 146-152
  SCIE KCI Scopus dColl.
• Unified Analytical Model for Switching Behavior of Magnetic Tunnel Junction IEEE ELECTRON DEVICE LETTERS, 2014, v.35 no.2, 193-195
  SCIE Scopus dColl.
• [학술지논문] A Unified Current-Voltage Model for Metal Oxide-Based Resistive Random-Access Memory MATERIALS, 2023, v.16 no.1 , 182-182
  SCIE
• [학술지논문] Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors IEEE ACCESS, 2023, v.11 no.1 , 15909-15920
  SCIE
• [학술지논문] Analysis of the transient body effect model for an LTPS TFT on a plastic substrate SOLID-STATE ELECTRONICS, 2021, v.175 no.1 , 107948-107948
  SCI
• [학술지논문] New Simulation Method for Dependency of Device Degradation on Bending Direction and Channel Length MATERIALS, 2021, v.14 no.20 , 6167-6167
  SCIE
• [학술지논문] Selected Bit-Line Current PUF: Implementation of Hardware Security Primitive Based on a Memristor Crossbar Array IEEE ACCESS, 2021, v.9 no.0 , 120901-120910
  SCIE
• [학술지논문] Analysis of Organic Light-Emitting Diode SPICE Models with Constant or Voltage-Dependent Components JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2020, v.20 no.8 , 4773-4777
  SCIE
• [학술지논문] Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM MICROMACHINES, 2020, v.11 no.11 , 952-952
  SCIE
• [학술지논문] Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM MICROMACHINES, 2020, v.11 no.2 , 228-228
  SCIE
• [학술지논문] Charge Based Current-Voltage Model for the Silicon on Insulator Junctionless Field-Effect Transistor JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2020, v.20 no.8 , 4920-4925
  SCIE
• [학술지논문] Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2020, v.20 no.8 , 4730-4734
  SCIE
• [학술지논문] Multibit-Generating Pulsewidth-Based Memristive-PUF Structure and Circuit Implementation ELECTRONICS, 2020, v.9 no.9 , 1446-1446
  SCIE
• [학술지논문] Optimization Considerations for Short Channel Poly-Si 1T-DRAM ELECTRONICS, 2020, v.9 no.6 , 1051-1051
  SCIE

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